LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity color_ram is
  port (clk : in std_logic;
		
		addr_r : in std_logic_vector(10 downto 0);
		rgb_a : out std_logic_vector(23 downto 0);
		rgb_b : out std_logic_vector(23 downto 0);
		
		addr_w : in std_logic_vector(10 downto 0);
		wr_en : in std_logic;
		cs : in std_logic;
		c_w : in std_logic_vector(7 downto 0));
end entity;

architecture rtl of color_ram is
	type memory is array(integer range<>) of std_logic_vector(7 downto 0);
	signal char_color : memory(1200 downto 0);
	subtype color is std_logic_vector(23 downto 0);
	type color_table is array(0 to 15) of color;
	signal color_val : std_logic_vector(7 downto 0);
	constant color_tab : color_table := color_table '(
		"000000000000000000000000",	-- zwart
		"000000000000000011111111",	-- rood
		"000000001111111100000000",	-- groen
		"000000001111111111111111",	-- geel
		"111111110000000000000000",	-- blauw
		"111111110000000011111111",	-- paars
		"111111111111111100000000",	-- cyaan
		"011111110111111101111111",	-- grijs
		"010000000100000001000000",	-- donkergrijs
		"100000001000000011111111",	-- lichtrood
		"100000001111111110000000",	-- lichtgroen
		"100000001111111111111111",	-- lichtgeel
		"111111111000000010000000",	-- lichtblauw
		"111111111000000011111111",	-- lichtpaars
		"111111111111111110000000",	-- lichtcyaan
		"111111111111111111111111");-- wit
		
begin
	process(addr_r, clk)
	begin
		if (rising_edge(clk)) then
			color_val <= char_color(to_integer(unsigned(addr_r)));
		end if;
	end process;

	rgb_a <= color_tab(to_integer(unsigned(color_val(3 downto 0))));
	rgb_b <= color_tab(to_integer(unsigned(color_val(7 downto 4))));
	
	process(clk, addr_w, c_w, wr_en)
	begin
		if (rising_edge(clk)) then
			if (unsigned(addr_w) < 1200) and (wr_en = '1') and (cs = '1') then
				char_color(to_integer(unsigned(addr_w))) <= c_w;
			end if;
		end if;
	end process;
end rtl;
